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Stuck at fault Model

akhil.neha.garg — Fri, 13 Jun 2008 08:25:43 CDT

Stuck-At Fault Models The stuck-at-0 model represents a signal that is permanently low regardless of the other signals that normally control the node. The stuck-at-1 model represents a signal that is permanently high regardless of the other signals that normally control the node. For example, Figure A-1 shows a two-input AND gate that has a stuck-at-0 fault on the output pin. Regardless of the logic level of the
two inputs, the output is always 0.
Figure A-1 Stuck-at-0 Fault on Output Pin of 2-input AND Gate
Detecting Stuck-At Faults The node of a stuck-at fault must be controllable and observable for the fault to be detected.A node is controllable if you can drive it to a specified logic value by setting the primary inputs to specific values. A primary input is an input that can be directly controlled in the test environment. A node is observable if you can predict the response on it and propagate the fault effect to the primary outputs where you can measure the response. A primary output is an output that can be directly observed in the test environment. To detect a stuck-at fault on a target node, you must do the following: • Control the target node to the opposite of the stuck-at value by applying data at the primary inputs. • Make the node’s fault effect observable by controlling the value at all other nodes affecting the output response, so the targeted node is the active (controlling) node. The set of logic 0s and 1s applied to the primary inputs of a design is called the input stimulus. The set of resulting values at the primary outputs, assuming a fault-free design, is called the expected response. The set of actual values measured at the primary outputs is called the output response. If the output response does not match the expected response for a given input stimulus, the input stimulus has detected the fault. To detect a stuck-at-0 fault, you need to apply an input stimulus that forces that node to 1. For example, to detect a stuck-at-0 fault at the output the two-input AND gate shown in Figure A-1, you need to apply a logic 1 at both inputs. The expected response for this input stimulus is logic 1, but the output response is logic 0. This input stimulus detects the stuck-at-0 fault. This method of determining the input stimulus to detect a fault uses the single stuck-at fault model. The single stuck-at fault model assumes that only one node is faulty and that all other nodes in the circuit are good. This type of model greatly reduces the complexity of fault modeling and is technology independent. In a more complex situation, you may need to control all other nodes to ensure observability of a particular target node. Figure A-2 shows a circuit with a detectable stuck-at-0 fault at the output of cell G2. Figure A-2 Simple Circuit With Detectable Stuck-At Fault

DFT Basics

akhil.neha.garg — Fri, 13 Jun 2008 08:19:00 CDT

Why Perform Manufacturing Testing?
Functional testing verifies that your circuit performs as it was intended to perform. For example, assume you have designed an adder circuit. Functional testing verifies that this circuit performs the addition function and computes the correct results over the range of values tested. However, exhaustive testing of all possible input combinations grows exponentially as the number of inputs increases. To maintain a reasonable test time, you must focus functional test patterns on the general function and corner cases. Manufacturing testing verifies that your circuit does not have manufacturing defects by focusing on circuit structure rather than functional behavior. Manufacturing defects include problems such as the following:

• Power or ground shorts
• Open interconnect on the die caused by dust particles
• Short-circuited source or drain on the transistor caused by metal spike-through

Manufacturing defects might remain undetected by functional testing yet cause undesirable behavior during circuit operation. To provide the highest-quality products, development teams must prevent devices with manufacturing defects from reaching the customers. Manufacturing testing enables development teams to screen devices for manufacturing defects. A development team usually performs both functional and manufacturing testing of devices.

What Are Fault Models?
A manufacturing defect has a logical effect on the circuit behavior. An open connection can appear to float either high or low, depending on the technology. A signal shorted to power appears to be permanently high. A signal shorted to ground appears to be permanently low. Many of these manufacturing defects can be represented using the industry-standard stuck-at fault model. Other faults can be modeled using the IDDQ, or quiescent current fault model.

Transition Fault Model

akhil.neha.garg — Fri, 16 May 2008 03:39:46 CDT

As the feature sizes of the devices decreased beyond 90nm the stuck at fault model was not enough to catch the newer defects. Hence, transition fault model became a major ingredient of the test suits.

Transition fault model

The Art to Test Home

akhil.neha.garg — Thu, 15 May 2008 06:05:06 CDT

This site is attributed to Design for Testability techniques of VLSI circuits. With the idea of an open forum I invite you people to have open discussions on the latest challenges of DFT.